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the time might not be equal and something might take longer. just buy another dryer (hardware) and we can increase output. actutal time takes longer than T/k , at we are not just summing one latch dealy if pipe line is 20 stage pipelined version we need to add 20 * latch delay. which cause individual instruction execution time will be increase but hopefully overall throughput will increase. ther..

destination address is chosen in instruction through 11~15bits. RegWrite control singal is ON (1) in R-type we have rs , rt to read so second mux choose read data2. ALUOp singal tells funct module to needed ALU operation with those 2 read registers. we don't read or write to memory so both of them are 0 result is written in Write register R-type doesn't change control flow so PC+4 is chosen dest..

ISA Design and Tradeoff ISA = specifies how the programmer sees the instructions to be executed , all major ISA today use Von-Nuemann Model. (x86 , ARM , MIPS ..) programmer might be able to adjust things in ISA but not in Microarchitecture there can be mutiple layers of ISA until it arrives at Microarchitecture Microarchitecture = how the underlying implementation actually executes instructions..

Data types MIPS supports 2's complement integers , unsigned integers , floating points Operate Instruction MIPS R-type instructions are binary operations I-type instructions = immediate + R-type instruction F type operation = floating-point operations. the bits before immediate is to identify whether next bits are immediate or register. In MIPS by seeing Opcode we can tell whether it is immediat..

Von Neumann model (LC-3 , MIPS) Memory the toal number of addresses is the address space LC-3 = 2^16 ==16bit addresses , a unique address for each 16 bit data word MIPS = 32 bit address , a unique address for each 32bit data word each data digit is 4bits so total 32bits. x86-64 = 48bit addresses Byte addressable memory 1 block is 1byte == 8bits. now you can access in units of byte. we are going ..

Delay is happens due to capacitance and resistance in a circuit. Rising and falling (1 -> 0) iuts different inputs have different delays changes in environment Aging of the circuit Contamination delay (tcd) = delay until Y starts changing , minimum possible delay Propagation delay (tpd) = delay until Y finishes changing , maximum possible delay need to wait until value get settle. even same gate..

Two main styles of HDL implementation Strcutural (Gate Level) Describe how modules are interconnected with gates Behavioral The module body contains functional description of the circuit Level of abstraction is higher than gate-level (but gate-level realizations) // You can assign partial buses wire [15:0] long bus; wire [7:0] shortbus; assign shortbus = longbus[12:5]; // Concatenating is by {} ..

Combinatinal circuit output depends only on current input We want circuits that produce output depending on current and past input values (circuit with memory) Latcehs and Flip-Flops very fast, parallel access very expensive (1 bit cost tens of transistors) we want to prevent forbidden state in the first place. D latches use Write enable we can prevent forbidden state issue, but more expensive. ..

Complement = variable with a bar over it Literal = variable or its complement Implicant = product of literal == (AB) , (ABC) ... Minterm = product (AND) taht includes all input variables == (ABC) , (A`BC) ... Sum of Products Form (SOP) First make truth table to Canonical From , than optimize it using axioms or other boolean expression tool. Product of Sums (POS) = Demorgan of SOP Building larger..

we are going to learn about microprocessors by programming FPGAs with Verilog. Transistors (devices , lower than logic gates) Mos Transistor Conductors (Metal) = cupper , gold , silver SemiConductors = Si , Ge ... they are neutral if they are pure. engineer some region to have + or - charges. Insulators (Oxide) = Rubber , ceramics , vaccum , air , glass MOS The width and length are related to th..