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Meltdown and Spectre Speculative execution =Doing something before you know that is needed leaves traces of secret data in the processor's cache = it brings data that is not supposed to be bought or accessed if there was no speculative execution. malicious program can infer this secret data. Row Hammer One can predictably induce bit flips in commodity DRAM chips you are only accessing particular..

even though x86 ISA had lots of drawbacks but software based on this ISA were already huge and transition to RISC ISA costs more. Intel's IA-64 and AMD's x86-64 IA-64 (Itanic) == Explicitly Parallel Instruction Computing (EPIC) + very long instruction word(VLIW) ISA + predication , speculative loading , other performance enhnacing technique but it had compatibilty issue with x86 and left big hol..

The Integer Execution Units simple / fast integer instructions == insturctions like add and sub require very few steps. these are the major portion of average program complex / slow ineger instructions == mutiple , division. have little portion compared to simple one. The G4e's IUs : Making the common case fast 3 simple / fast integer execution units - SIUa, SIUb, SIUc == each of 3 fast iUs is f..

Pentium 4's speed addiction P4 had 20stages in basic pipeline. which made it have high relative frequency. but there are limits to how deeply you can pipeline an architecture before you begin to reach a point of diminishing returns. 1. deeper pipeline means increase in instruction execution time 2. processor's clock speed must increase in proportion to tis pipeline depth regradless of the drawba..

601's pipeline has a classic 4 stage RISC integer pipeline: fetch, decode/dispatch, exectue , write back Instruction queue == is used mainly for dectecting an dealing with branches. if branch unit has enough information to resolve the branch immediately it is simply deleted from the instruction queue and replaced with the instruction located at the branch target. (branch folding) When a branch i..

pentium shares 4 stages in common : Fetch , Decode-1 , Decode-2 , Write when instruction reaches the execute phase it enters a more specialized pipeline. depth of pipeline can be different Petium's basic integer pipeline has 5 stages 1. Prefetch/Fetch == fetched from instruction cache and aligned in prefetch buffers for decoding. 2. Decode-1 == based on set of hardware-based rules instructions a..

even though we have 2 ALU(parallel) the interface represents a sequential execution machine. so main memory still sees one sequential code stream, one data stream, and one results stream. DLW-2 fetches instructions from memory in groups of 2 in one clock cycle. but if the first instruction is branch, the second instruction has to be discarded. causing bubble into the pipeline. There are 2 kinds ..

In Pipeline we have 4 stages Fetch , Decode , Execute, Write In this chapter we assume every phase take 1ns pipeline doesn't speed up instruction execution time, but speed up program execution time(entire program) number of stage == pipeline' speed up rate // 4 stage , 4 times faster // which means if we slice more stage into more stage we can get better result but does the eightfold increase in..

The English words in a program, like add, load, and store, are mnemonics(meaning they’re easy for people to remember), and they’re all mapped to strings of binary numbers, called opcode mode bit == if the mode bit is set to 0 then the instrction is register -type instruction else immediate type the last six bits(10~15) are paeeded with 0s because they are not needed 3 kinds of machine language f..