Lecture 7b: HW Description Lang. & Verilog

Two main styles of HDL implementation 

Strcutural (Gate Level)

Describe how modules are interconnected with gates

Behavioral

The module body contains functional description of the circuit

Level of abstraction is higher than gate-level (but gate-level realizations)

 

 

// You can assign partial buses
wire [15:0] long bus;
wire [7:0] shortbus;
assign shortbus = longbus[12:5];

// Concatenating is by {}
assign y = {a[2],a[1],a[0],a[0]};

// Possible to define multiple copies
assign x = {a[0], a[0] , a[0] , a[0]};
assign y = {4{a[0]}}

an example of module abstraction

 

you can use small moudle as instance and make bigger module. 

 

 

module example (a,b,c,y);
	input a;
	input b;
	input c;
	output y;

assign y = ~a & ~b &~c | a & ~b & ~c | a & ~b & c;

endmodule

realization come true by gates.

module and8 (input [7:0] a, output y);
assign y = &a;

// assign y = a[7] & a[6] ... a[1] & a[0];
endmodule

reduction operators in behavioral verilog

 

Z is floating bits for Tri State Buffers.

 

Synthesis

Modern tools are able to map synthesizable HDL code into low level cell libraries.

They can perform many optimization.

 

Simulation

Allows the behavior of the circuit to be verified without actually manufacturing the circuit

 

using last one is more preferable way.

 

Sequential Logic 

module flop (input clk, input [3:0] d, output reg [3:0] q);

aways @ (posedeg clk)
	q <= d // pronounced "q gets d"

endmodule

D Flip Flop , when the clock is rising (0 ->1) , the value of d is copied to q.

notice assign statement is not used.  <=  is non blocking assignment. 

Assigned variables need to be declared as "reg" but this doesn't necesarily mean that the value is a register.

 

Asynchronous and Synchronous Reset

Reset signals are used to initialize the hardware to a known state 

 

Asynchronous Reset

• reset signal is sampled indepedent of the clock
• sensitive to glitches , may have metastability issues

module flop_ar (input clk, input reset, input [3:0] d, output reg [3:0] q);

always @ (posege clk , negedge reset)
	begin
		if (reset == 0) q <= 0; // when reset
		else q<=d; // when clk
	end
endmodule

2 events can trigger the process , rising edge on clk , falling edge on reset

 

Synchronous Reset

• reset signal is sampled with respect to the clock.
• the reset should be active long enough to get sampled at the clock edge

module flop_sr (input clk, input reset, input [3:0] d, output reg [3:0] q);

always @ (posege clk)
	begin
		if (reset == 0) q <= 0; // when reset
		else q<=d; // when clk
	end
endmodule

 

 

module comb(input inv, input [3:0] data, output reg [3:0] result);

  always @ (inv ,data) // trigger with inv, data
    if (inv) result <= ~data; // result is inverted data
    else result <= data; // result is data

endmodule

always block get be use in combination logic.  

result is assigned a value in all cases of the if .. else block , always.

 

always block defines cominational logic if all outputs are always (continuously) updated

first one's out_b can change continously if enable is 0 , it will stay same, like memory.

second one both of out_a , out_b will stay the same if enable is zero.

 

this is combinational logic because segments get change continuously no matter what.

 

 

 

module divide3FSM (input clk input reset, output q);
  
  reg [1:0] state, nextstate;

  parameter S0 = 2'b00;
  parameter S1 = 2'b01;
  parameter S2 = 2'b10;

  always @ (posedge clk , posedge reset) // state register
    if (reset) state <= S0;
    else state <= nextstate;
  
  always @ (*)
    case (state)
      S0: nextstate = S1;
      S1: nextstate = S2;
      S2: nextstate = S0;
      default: nextstate = S0;
    endcase
  
  assign q = (state == S0);

endmodule