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Sram is used for L1,L2 caches which is more expensive. having higher bandwidth. Cache access index into the tag and data stores with index bits in address check valid bit in tag store compare tag bits in address with the stored tag in tag store every block ( for example 00010 , 01010 , 10010, 11010 4 blocks) can be mapped to exact same place. and with tag we can find which cluster of block is th..

Promgramming Model = how the programmer expresses the code e.g) Sequential (von Neumann) , Data Parallel (SIMD) , Dataflow, Multi-threaded (MIMD, SPMD) Execution Model = how the hardware executes the code underneath e.g) Out of order execution , Vector processor , Array processor , dataflow processor, Multithreaded processor GPU = SPMD(Single program Multiple data) model implemented by a SIMD pr..

SISD = Single instruction operates on single data element SIMD = Single instruction operates on mutiple data elements (Array processor, Vector processor) MISD = Mutiple instructions operate on single data element (systolic array processor, streaming processor) MIMD = Multiple instructions operate on mutiple data elements (multiple instruction streams) ,Multiprocessor , Multithreaded processor. n..

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Branch Problem = Next fetch address after a control-flow instruction is not determined after N cycels in a pipelined processor so we try to predict branch target address. based on previous history we might have some address in BTB. if not we just add insturction size to current PC and take that to next PC. Simple Branch Prediction Schemes Compile time (Static) Assuming always not taken Assuming ..

Reverse Engineer and create Data flow by looking at first picture we can create second picture's right , which is data flow graph. and by looking at data flow graph we can create left instructions. Out of Order Execution with Precise Exception user reorder buffer to reorder instructions before committing them to architectural state instruction updates the Register alias table(RAT, frontend regis..

for example, we are trying to excute the red instruction "Add R3 R4". we need R3 so we check reorder buffer whether it is valid or not if not valid we stall the instruction. if valid we can take bypass and take value from reorder buffer. notice below red instruction there are no depdency. but since in red instruction R3 has to wait for IMUL instrction (8 cycles) , other 3 blue line instruction s..

this shows we might be waisting 3 instruction due to branch instruction. we need to flush 3 instruction if branch codition is right. we want to know more quickly whether the condition of the branch instruction is satisfied. we can move target address checking more ealier. so now we can reduce nubmer of instruction to flush when target matches. Advantage = reduced CPI( cycles per instruction ) Di..

the time might not be equal and something might take longer. just buy another dryer (hardware) and we can increase output. actutal time takes longer than T/k , at we are not just summing one latch dealy if pipe line is 20 stage pipelined version we need to add 20 * latch delay. which cause individual instruction execution time will be increase but hopefully overall throughput will increase. ther..

destination address is chosen in instruction through 11~15bits. RegWrite control singal is ON (1) in R-type we have rs , rt to read so second mux choose read data2. ALUOp singal tells funct module to needed ALU operation with those 2 read registers. we don't read or write to memory so both of them are 0 result is written in Write register R-type doesn't change control flow so PC+4 is chosen dest..