Lecture 11: Microarchitecture I

 ISA Design and Tradeoff

 

ISA = specifies how the programmer sees the instructions to be executed , 

all major ISA today use Von-Nuemann Model. (x86 , ARM  , MIPS ..)

programmer might be able to adjust things in ISA but not in Microarchitecture

there can be mutiple layers of ISA until it arrives at Microarchitecture

 

Microarchitecture = how the underlying implementation actually executes instructions

the execution model of almost all implementation are very different

• Piplelined instruction execution: Intel 80486 uarch
• Mutiple insturctions at a time : Intel Pentium uarch

 Implementation of the ISA under specific design constraints and goals.

design point determined by the Problem space (applciation space).

 

 

 these transition is not visible in ISA point of view(programmer cannot recognize).

Microarchtiecture implements how AS -> AS` is transformed , and there are many ways to do it. 

we can also have mutiple state not just AS -> AS` , but AS -> AS+MS1 -> AS +MS2 . . .  -> AS`

 

Instruction processing engine consist of 2 components.

• Datapath = hardware elements that deal with and transform data signals.
• Control logic = hardware elements that determine control signals 

 

 

Single Cycle Machine

• each instruction takes a single clock cycle
• the slowest instruction determines cycle time = log clock cycle time
• everything related to an instruction happens in one clock cycle (serialized processing)

 

Mutil Cycle Machine

• instruction processing broken into mutiple cycle/stages.
• the slowest stage determines cycle
• Latency of control processing can be overlapped with latency of datapath operation (more parallesim)

 

CPI = number of cycles per instruction 

 

Building R-type ALU with Datapath

translating semantics into combination state logic. first line (add) , second line (PC update) happen parallely.

inside ALU module 

there can be lot of arithmatic operation for given input.

base on R type instruction implementation we will going to add I type instruction.

by adding mux before ALU we can process both I type and R type instruction. if incoming instruction is I-Type mux will choose sign extended data and add with data1. otherwise it will just add data1 and data2.

 

we also add Memory module to perform "Load" and "Store" instructions. at lower mux if it is "Load" we read data from memory , if it is "Store" gets data from ALU result.

 

"Jump" instruction doesn't affect memory part it only affect with PC.

with isJ mux, if is not jump we just add 4 to given PC , if it is jump we take top 4 bit from PC + bottom 26 bits from instruction. and update PC , if it is JR we take our next PC from our register.

 

Inside orange ALU operation we do subtraction to see wether given register value is same.

above orange AND GATE it decide if (given instruction == Branch and branch condition evaluate to true) then result of and gate will be one and it controls above mux 

left ALU is getting PC+4 and sign extended immediate instruction *4(shift by 2)  and result is target address.

right most mux takes PC+4 and target address and decide if instruction is not branch.