Lecture 14: Pipelining Issues

this shows we might be waisting 3 instruction due to branch instruction.

we need to flush 3 instruction if branch codition is right. 

we want to know more quickly whether the condition of the branch instruction is satisfied.

we can move target address checking more ealier.

so now we can reduce nubmer of instruction to flush when target matches.

 

Advantage = reduced CPI( cycles per instruction )

Disadvantage =  potential increase in clock cycle time, additional hardware cost.

 

 

fastest of the 3 MIPS architectures is pipelined.

however , even though we have 5 fold pipelining , it is not 5 times faster than single cycle.

 

 

Software based instruction scheduling 

• static scheduling
• before runtime
• for example in branch prediction we can't know what the previous branch choice was
• estimate value that can be know only in runtime by profiling

 

Hardware based instruction scheduling

• dynamic scheduling
• during runtime
• can collect information during runtime 

 

 

execution stage may take mutiple cycels to finish.

 

 

Exceptions

• internal to the running thread , like instructions
• need to be handle when detected
• enable recovery from exception
• enable restartable processes 

 

Interrupts

• external to the running thread
• due to Von Neumann architecture , single processor , need to interrupt to do something else.
• can hanlde when convenient , except for high priority ones

 

 

in case for independent operation , assuming we checked dependency , we can store our result in reorder buffer and a make every instruction sequential.

we might want to use reorder buffer 's value at some point. but it is differernt from reading from register files.

as we can see unlike register files we need to check if given reorder buffer has our source register value(address ,like R3).

to avoid searching we can use concept of indirection.

the value of R3 will be filled with garbage , and real value lies on reorder buffer , in this case 131. now we don't need to search.