Lecture 19: SIMD Processors

SISD = Single instruction operates on single data element

SIMD = Single instruction operates on mutiple data elements (Array processor, Vector processor)

MISD = Mutiple instructions operate on single data element (systolic array processor, streaming processor)

MIMD = Multiple instructions operate on mutiple data elements (multiple instruction streams) ,Multiprocessor , Multithreaded processor.

 notice in vector processor We can execute the instruction as soon as we read an element of the array.

 

VLIW(Very Long Instruction Word) = Mutiple independent operations packed together by the compiler

Array Processor = Single operation on mutiple (different) data elements.

 

 

Basic requirements for vector processor

• Need to load/store vectors = vector registers (contain vectors)
• Need to operate on vectors of different lengths -> vector length (VLEN)
• Elements of a vector might be stored apart from each other in memory -> vector stride register (VSTR)

 

Pros

• No dependencies within a vecotr
• Each instruction generates a lot of work
• Highly regular memory access pattern
• No ned to explicitly code loops

Cons

• Works (only) if parallelism is regular (data/SIMD parallelism)
• very inefficient if parallelism is irregular
• Memory (bandwidth) can easily become a bottleneck, especially if compute/memory operation balance is not maintained, data is not mapped appropriately to memory banks.

 

 

MAR will have to be decoded , with bank memory system we can have much smaller decoder for each bank.

assume that accessing to memory and achieving data takes 11 cycles (with stride == 1). than after 11 cycles we can achieve address 0's data. at 12 cycles we can achieve address 1's data and so on.

notice bank latency (here 11cycles) needs to be lower than number of bank.

also stride matters if stride is 16 than every memory address will be in Bank 0 than we cannot benefit from vector processor's method.