Lecture 2b: Mysteries in Comp. Arch.

Meltdown and Spectre

Speculative execution =Doing something  before you know that is needed

leaves traces of secret data in the processor's cache = it brings data that is not supposed to be bought or accessed if there was no speculative execution.

malicious program can infer this secret data.

 

Row Hammer

One can predictably induce bit flips in commodity DRAM chips  

you are only accessing particular row but when this keep happens other rows that are near to accessed row get their bit flips due to electrical inference between the cells since they are so close.

refreshing entire memory frequently can be solution but it loose perfomance.  

 

DRAM Refresh

DRAM capacitor charge leaks over time so it need to be refreshed which cause performance degradation.

Solution = RAIDR

1. Profiling = identify the retention time of all DRAM rows
2. Binning = store rows into bins by retention time (Bloom Filters) 
3. Refreshing = memory controlle refreshes rows in different bins at different rates

 

 

Problem 

Even with 2core,  application performance were getting worse.

DRAM Memory Controller was scheduling unfairly since matlab has more request than gcc , prioritizing over gcc request.

row conflict access takes significantly longer than a row-hit access, so current controller take advange of this fact.

FR-FCFS (policy)

1. Row-hit-first = service row hit memory accesses first (not fair for apps with high row buffer locality)
2. oldest-first = then service older accesses first (not fair for memory intensive applications)

Taking advantages of memory controller policy.

 

FPGA (field progmmable gate array) 

accelerates DNN inferencing , with applications in CV and NLP , AWS Ec2 F1 has FPGAs to enable delivery of custom hardware accelerations.

fill the gap between software and hardware