Computer Architecture/Inside the Machine

Pipelined Execution (Chapter3)

Tony Lim 2020. 12. 27. 16:25
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In Pipeline we have 4 stages Fetch , Decode , Execute, Write In this chapter we assume every phase take 1ns 

wasting resources but simple to design // completed instructions box is not real it is just representation for clear view
4stages == pipeline depth // notice clock cycle time has shrunk // pipeline works in same duration of stages

pipeline doesn't speed up instruction execution time, but speed up program execution time(entire program)

number of stage == pipeline' speed up rate // 4 stage , 4 times faster // which means if we slice more stage into more stage we can get better result

but does the eightfold increase in completion rate translate into an eightfold performance increase? Not exactly

program execution time = number of instructions in programs / instruction completion rate

therer can be bubble and it decrease average instruction throughput
10 cycles of bubble feels fine?

but processor can spend about 100ns waiting on data form main memory. but with 3GHz cpu that has clock time of fraction of nano second which means few thousand clock cycles of bubble. 

In reality slowest stage int the pipeline will determine the length o fthe CPU's clock cycle and thus the length of every pipeline stage. so designer must distribute the work of processing an isntruction evenly to each stage.

pipline perfomance depends on 2 things 

1. Pipeline stalls must be avoided

2. Pipeline refills mut be avoided. 

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