Lecture 9: Von Neumann Model ISA LC3 MIPS
Von Neumann model (LC-3 , MIPS)
Memory
the toal number of addresses is the address space
LC-3 = 2^16 ==16bit addresses , a unique address for each 16 bit data word
MIPS = 32 bit address , a unique address for each 32bit data word
each data digit is 4bits so total 32bits.
x86-64 = 48bit addresses
Byte addressable memory
1 block is 1byte == 8bits. now you can access in units of byte.
we are going to deal with little endian convention
2 registers that are necessary to access memory
Memory Address Register (MAR)
Memory Data Register (MDR)
To read = Load the MAR with the address , Data is palced in MDR
To write =Load the MAR with the address and the MDR with the data , activate enable signal
Processing Unit
MUX + Logic function + ALU ....
ALU processes quantities that are referred to as words. (MIPS == 32bits)
typically 1 register contains one word.
LC-3 has 8 general purpose registers (GPR) = R0 to R7 (3bit register number)
MIPS has 32 registers (register size == word length == 32bits)
Control unit
it conducts the step by step process of excuting every instruction in a program.
Insturction register (IR) = instruction that is about to execute.
Insturciton pointer(IP), Progam counter(PC) = contain the address of the next insturciton to execute.
Von Neumann Model's 2 key properties
Stored Program
- Insturctions stored in a linear memory array
- Memory is unified between instruction an ddata , the interpretation of a stored value depends on the control signals
Sequential insturction processing
- One instruction prcoessed (fetched , executed , completed) at a time.
- Program counter (insturction pointer) identifies the current instruction.
- Program counter is advanced sequentially except for control transfer instructions.
if word addresable memroy PC increments by 1 (in LC3)
if byte addressable memory PC increments by (word length) 4 (32bits/4blocks/2bits) in MIPS
The Instruction
Instructions are words in the language of computer
Instruction Set Architecture (ISA) is teh vocabulary
Operate Instructions = execute instructions in the ALU
Data movement insturctions = Read from or wirite to memory
Control flow instructions = Change the sequence of execution
8 because we want to point at A[2] and since MIPS in this case it is byte-addressable memory so each block is 4byte so thrid one starts at 8byte + default address.
Instruction Cycle (in order)
Fetch
- Load the MAR with the contents of the PC, and increment the PC // both of them happens concurrently , done in one clock cycle.
- Interrogate memory. This results the instruction to be placed in the MDR
- Load the IR with th econetns of the MDR // MDR goes into IR
Decode
identifies the instruction , 4 to 16 decoder , find out what are op,rs,rt, imm ...
Evaluate Address
computes the address of the memory location that is needed to process the instruction.
given rs or rt register's value and immediate from decoder it performs add to evaluate address.
Fetch Operands
obtains the source operands needed to process the instruction.
load address to register (LDR)
- load MAR with the address calculate din Evaluate Address
- read memory , placing source operand in MDR
Add
- Obtain the source operands from the register file
- this phase can be done at the same time the instruction is being decoded.
Exectue
Store Result
